Section: Software and Platforms

FloPoCo

Participants : Florent de Dinechin [correspondant] , Matei Istoan.

The purpose of the FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm [32] . FloPoCo is a generator of operators written in C++ and outputting synthesizable VHDL automatically pipelined to an arbitrary frequency.

2013 saw more work on the bit-heap framework [28] , [18] . In addition, several new operators were added, in particular for fixed-point sine, cosine [21] and arctangent.

Version 2.5.0 was released in 2013.

Among the known users of FloPoCo are U. Cape Town, U.T. Cluj-Napoca, Imperial College, U. Essex, U. Madrid, U. P. Milano, T.U. Muenchen, T. U. Kaiserslautern, U. Paderborn, CalTech, U. Pernambuco, U. Perpignan, U. Tohoku, U. Tokyo, Virginia Tech U. and several companies.

URL: http://flopoco.gforge.inria.fr/

• Version: 2.5.0 (June 2013)

• APP: IDDN.FR.001.400014.000.S.C.2010.000.20600 (version 2.0.0)

• License: pending, should be GPL-like.

• Type of human computer interaction: command-line interface, synthesizable VHDL output.

• OS/Middleware: Linux, Windows/Cygwin.

• Required library or software: MPFR, flex, Sollya.

• Programming language: C++.

• Documentation: online and command-line help, API in doxygen format, articles.